--
-- Copyright CESR CNRS 
-- 	      9 avenue du Colonel Roche
-- 	      31028 Toulouse Cedex 4
--
-- Contributor(s) : 
--
--  - Bernard Bertrand 
--  
--
-- This software is a computer program whose purpose is to implement a spacewire 
-- link according to the ECSS-E-50-12A.
--
-- This software is governed by the CeCILL-C license under French law and
-- abiding by the rules of distribution of free software.  You can  use, 
-- modify and/ or redistribute the software under the terms of the CeCILL-C
-- license as circulated by CEA, CNRS and INRIA at the following URL
-- "http://www.cecill.info". 
--
-- As a counterpart to the access to the source code and  rights to copy,
-- modify and redistribute granted by the license, users are provided only
-- with a limited warranty  and the software's author,  the holder of the
-- economic rights,  and the successive licensors  have only  limited
-- liability. 
--
-- In this respect, the user's attention is drawn to the risks associated
-- with loading,  using,  modifying and/or developing or reproducing the
-- software by the user in light of its specific status of free software,
-- that may mean  that it is complicated to manipulate,  and  that  also
-- therefore means  that it is reserved for developers  and  experienced
-- professionals having in-depth computer knowledge. Users are therefore
-- encouraged to load and test the software's suitability as regards their
-- requirements in conditions enabling the security of their systems and/or 
-- data to be ensured and,  more generally, to use and operate it in the 
-- same conditions as regards security. 
--
-- The fact that you are presently reading this means that you have had
-- knowledge of the CeCILL-C license and that you accept its terms.
--

----------------------------------------------------------------------------------------
--	LENGTH set wide for deep.
--	First data is present " on out put before first read
--	9/10/2009
--	B.Bertrand
--	credit variable is removed
----------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

use work.spacewire_Pack.all;

entity tx_credit_manager is
port(
		Reset_n : in std_logic;
		Clk : in std_logic;
		State : in FSM_State;

		-- Credit

		fct_n : in std_logic;     -- allow 7 reads in the fifo
		short_send_eop_rising : in std_logic;
		fct_Full_n : out std_logic;  -- true when all the FIFO has been allowed to be read
		Credit_Empty_n : out std_logic;
		
		-- Data Input

		Wr_n : in std_logic;

		-- Data Output

		Rd_n : in std_logic;
		
		Credit : out integer range 0 to MAX_CREDIT

	);
end entity;

architecture T1 of tx_credit_manager is

signal signal_Credit : integer range 0 to MAX_CREDIT;

begin

manager:	process(State, reset_n, Clk)
begin
if Reset_n = '0' or State = ErrorReset
then
fct_full_n <= '1';
signal_Credit <= 0;
else
	if Clk='1' and Clk'event
	then
	
		if fct_n='0' and signal_Credit <= MAX_CREDIT - 8  and ( State = Connecting or State = Run ) 
		then	
			if Rd_n = '1'
			then	--	increase credit don't read data
			signal_Credit <= signal_Credit + 8;
			else	--	increase credit read data
			signal_Credit <= signal_Credit + 7;
			end if;
		else
			if (fct_n = '0' and  (State = Run or State = connecting)) and (signal_Credit >= MAX_CREDIT)  
			then 
			fct_full_n <= '0';	--	error appear. 
			else
				if Rd_n = '0'
				then	--	read data
				signal_Credit <= signal_Credit - 1;
				end if;	
			end if;
		end if;
	
	end if;	--	clk
end if;	--	reset
end process;

Credit_Empty_n <= '0' when signal_Credit = 0 else '1';

Credit <= signal_Credit;

end T1;