--
-- Copyright CESR CNRS 
-- 	      9 avenue du Colonel Roche
-- 	      31028 Toulouse Cedex 4
--
-- Contributor(s) : 
--
--  - Bernard Bertrand 
--    
--
-- This software is a computer program whose purpose is to implement a spacewire 
-- link according to the ECSS-E-50-12A.
--
-- This software is governed by the CeCILL-C license under French law and
-- abiding by the rules of distribution of free software.  You can  use, 
-- modify and/ or redistribute the software under the terms of the CeCILL-C
-- license as circulated by CEA, CNRS and INRIA at the following URL
-- "http://www.cecill.info". 
--
-- As a counterpart to the access to the source code and  rights to copy,
-- modify and redistribute granted by the license, users are provided only
-- with a limited warranty  and the software's author,  the holder of the
-- economic rights,  and the successive licensors  have only  limited
-- liability. 
--
-- In this respect, the user's attention is drawn to the risks associated
-- with loading,  using,  modifying and/or developing or reproducing the
-- software by the user in light of its specific status of free software,
-- that may mean  that it is complicated to manipulate,  and  that  also
-- therefore means  that it is reserved for developers  and  experienced
-- professionals having in-depth computer knowledge. Users are therefore
-- encouraged to load and test the software's suitability as regards their
-- requirements in conditions enabling the security of their systems and/or 
-- data to be ensured and,  more generally, to use and operate it in the 
-- same conditions as regards security. 
--
-- The fact that you are presently reading this means that you have had
-- knowledge of the CeCILL-C license and that you accept its terms.
--

---------------------------
--B.Bertrand
--9/10/2009
--credit variable is removed
----------------------------


library ieee;
use ieee.std_logic_1164.all;

use work.Spacewire_Pack.all;

entity rx_credit_manager is
	generic(
		LENGTH : integer	
	);	
	port(
		Reset_n : in std_logic;
		Clk : in std_logic;
		State : in FSM_State;

		-- Credit

		Credit_Rd_n : in std_logic;     -- allow 8 writes in the fifo
		Credit_Empty_n : out std_logic;  -- true when all the FIFO has been allowed to be written
		credit_error_n : out std_logic;

		-- Data Input

		Wr_n : in std_logic;
		short_got_EOP_n : in std_logic;
		
		-- Data Output

		Rd_n : in std_logic;
		
		Credit : out integer range 0 to MAX_CREDIT

	);
end entity;

architecture R1 of rx_credit_manager is

signal signal_Credit : integer range 0 to MAX_CREDIT;
signal Cpt : integer range 0 to LENGTH;

begin

manager:	process(State, reset_n, Clk)
begin
if Reset_n = '0' or State = ErrorReset
then
credit_error_n <= '1';
signal_Credit <= 0;
else
	if Clk='1' and Clk'event
	then
		if  signal_Credit <= MAX_CREDIT - 8 and ( State = Connecting or State = Run ) and Credit_Rd_n = '0'
		then 	--	increase credit
			if Wr_n = '1'   
			then	--	increase credit
			signal_Credit <= signal_Credit + 8;
			else
				if Wr_n = '0'  
				then 
					if signal_Credit /= 0
					then  -- write and increase credit      		
					signal_Credit <= signal_Credit + 7;
					else
					credit_error_n <= '0';	--	error appear
					end if;
				end if;
			end if;
		else
			if Wr_n = '0'  
			then
				if signal_Credit /= 0
				then  -- write        		
				signal_Credit <= signal_Credit - 1;
				else
				credit_error_n <= '0'; --	error appear
				end if;
			end if;
		end if;
	end if;	--	clk
end if;	--	reset
		
end process;

Credit_Empty_n <= '0' when ((signal_Credit > (MAX_CREDIT - 8))  or (cpt > LENGTH - (MAX_CREDIT + 8))) and ( State = Connecting or State = Run ) else '1';

process(State, reset_n, Clk)
begin
if Reset_n = '0' or State = ErrorReset
then
Cpt <= 0;
else
	if Clk='1' and Clk'event
	then
		if Rd_n='0'
		then
		Cpt <= Cpt - 1;
		else
			if Wr_n = '0'
			then
			Cpt <= Cpt + 1;
			end if;
		end if;
	end if;
end if;	
end process;

Credit <= signal_Credit;

end R1;