vcom Spacewire_Pack.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Compiling package spacewire_pack
# -- Compiling package body spacewire_pack
# -- Loading package spacewire_pack
vcom emu_pack.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package spacewire_pack
# -- Compiling package emu_pack
# -- Compiling package body emu_pack
# -- Loading package emu_pack
vcom emu_spwr_pack.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package spacewire_pack
# -- Loading package emu_pack
# -- Compiling package emu_spwr_pack
# -- Compiling package body emu_spwr_pack
# -- Loading package emu_spwr_pack
vcom emu_spwr.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package spacewire_pack
# -- Loading package emu_pack
# -- Loading package emu_spwr_pack
# -- Compiling entity emu_spwr
# -- Compiling architecture rtl of emu_spwr
vcom Rx.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package spacewire_pack
# -- Compiling entity rx
# -- Compiling architecture r1 of rx
vcom Tx.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package spacewire_pack
# -- Compiling entity tx
# -- Compiling architecture t1 of tx
vcom Rx_Fifo.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package spacewire_pack
# -- Compiling entity rx_fifo
# -- Compiling architecture r1 of rx_fifo
vcom Tx_Fifo.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package spacewire_pack
# -- Compiling entity tx_fifo
# -- Compiling architecture t1 of tx_fifo
vcom fsm.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package spacewire_pack
# -- Compiling entity fsm
# -- Compiling architecture rtl of fsm
vcom width_to_short_n.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity width_to_short_n
# -- Compiling architecture rtl of width_to_short_n
vcom twodomainclock.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package spacewire_pack
# -- Compiling entity twodomainclock
# -- Compiling architecture rtl of twodomainclock
# -- Loading entity width_to_short_n
vcom tb_check_spwr_ip.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package spacewire_pack
# -- Loading package emu_pack
# -- Compiling entity tb_check_spwr_ip
# -- Compiling architecture t1 of tb_check_spwr_ip
# -- Loading package emu_spwr_pack
# -- Loading entity emu_spwr
# -- Loading entity rx
# -- Loading entity rx_fifo
# -- Loading entity twodomainclock
# -- Loading entity tx_fifo
# -- Loading entity tx
# -- Loading entity fsm
# ** Warning: tb_check_spwr_ip.vhd(2211): Duplicate signals in sensitivity list.
vcom test43.vhd
# Model Technology ModelSim SE vcom 5.8d Compiler 2004.06 Jun 12 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity test43
# -- Compiling architecture rtl of test43
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Loading package spacewire_pack
# -- Loading package emu_pack
# -- Loading entity tb_check_spwr_ip
vsim work.test43
# vsim work.test43 
# //  ModelSim SE 5.8d Jun 12 2004 
# //
# //  Copyright Model Technology, a Mentor Graphics Corporation company, 2004
# //                         All Rights Reserved.
# //                   UNPUBLISHED, LICENSED SOFTWARE.
# //         CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# //        PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
# Loading c:\Modeltech_5.8d\win32/../std.standard
# Loading c:\Modeltech_5.8d\win32/../ieee.std_logic_1164(body)
# Loading c:\Modeltech_5.8d\win32/../ieee.std_logic_arith(body)
# Loading c:\Modeltech_5.8d\win32/../ieee.std_logic_unsigned(body)
# Loading c:\Modeltech_5.8d\win32/../std.textio(body)
# Loading c:\Modeltech_5.8d\win32/../ieee.std_logic_textio(body)
# Loading work.spacewire_pack(body)
# Loading work.emu_pack(body)
# Loading work.test43(rtl)
# Loading work.emu_spwr_pack(body)
# Loading work.tb_check_spwr_ip(t1)
# Loading work.emu_spwr(rtl)
# Loading work.rx(r1)
# Loading work.rx_fifo(r1)
# Loading work.twodomainclock(rtl)
# Loading work.width_to_short_n(rtl)
# Loading work.tx_fifo(t1)
# Loading work.tx(t1)
# Loading work.fsm(rtl)
run 30000us
# ------ERROR RESET STATE------- 
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 1  Instance: /test43/test/fsm_component/fsm
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 1  Instance: /test43/test/fsm_component/fsm
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 1  Instance: /test43/test/fsm_component/fsm
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 1  Instance: /test43/test/fsm_component/fsm
# ------error wait state ------- 
# ------ready state------- 
# ------rx generate error parity------- 
# ------ERROR RESET STATE------- 
# ------error wait state ------- 
# ------ready state------- 
# ------started state------- 
# ------connecting state------- 
# ------ERROR RESET STATE------- 
# ------rx generate error parity------- 
# ------error wait state ------- 
# ------char is appear in rx------- 
# ------ERROR RESET STATE------- 
# ------error wait state ------- 
# ------ready state------- 
# ------started state------- 
# 
# <EOF> 
